Cadence vlsi design software free download
To my coworkers, for their advice and assistance. To my adviser, for his attention, encouragement, guidance and support. iiģ To my family, for their love and support.
Fundamental concepts and major components of SerDes are covered, as well as the design flow of a Serializer from unit block design in Cadence Virtuoso to simulation in HSPICE, using a 45nm CMOS process. As a result, this thesis serves as an introduction to SerDes for beginners as well as a tutorial of mixed-signal integrated circuit design, using an example of a Serializer circuit.
Designing a robust, lower power SerDes that functions properly at high speed is very challenging and requires knowledge from several different areas. SerDes is very beneficial because it solves the problems of many traditional parallel data links and reduces the number of I/O pins and cost for connectors and cables.
Cadence vlsi design software free download serial#
A Serializer/Deserializer (SerDes) is such a device that takes the parallel data link input and condenses it into fewer lines of serial stream which would then deserialized and output as the original recovered parallel data. Serial I/O has the advantage of faster speed, less interference between adjacent links, fewer pin counts and thus lower packaging costs. As integrated circuits (IC) become smaller size and faster speed, traditional parallel communication is not suitable due to cross-talk, data-skew, and other problems related to electronic packaging and signal integrity. Schutt-AinéĢ ABSTRACT Input/output (I/O) has always played an important part in modern high speed applications. 1 HIGH SPEED CMOS SERDES DESIGN AND SIMULATION USING CADENCE VIRTUOSO AND HSPICE BY JERRY YANG THESIS Submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical and Computer Engineering in the College of Engineering of the University of Illinois at Urbana-Champaign, 2013 Urbana, Illinois Adviser: Professor José E.